-- Relogio

library ieee;
use ieee.std_logic_1164.all;
use work.PCT_RELOGIO.all;

entity RELOGIO is
	port(
	SET : in std_logic;
	LOAD : in std_logic;
	INC : in std_logic;
	RESET : in std_logic;
	CLK : in std_logic;
	PRESETS : in std_logic_VECTOR(7 downto 0);
	S5, S4, S3, S2, S1, S0 : out std_logic_vector(6 downto 0);
	ESTADO : out std_logic_vector(2 downto 0)
	);
end RELOGIO;

architecture DT_FLOW of RELOGIO is
signal AT : std_logic;
signal COUNT : std_logic;
signal ENT_DEMUX : std_logic_vector(1 downto 0);
signal S_HORA, S_MINUTO, S_SEGUNDO : std_logic;
signal CLK_HORA, CLK_MINUTO : std_logic;
signal QCLK : std_logic;

begin

	MAQUINA : MDE port map (SET, RESET, QCLK, AT, COUNT, ENT_DEMUX);
	DEMUX1 : DEMUX port map (ENT_DEMUX, S_HORA, S_MINUTO, S_SEGUNDO);
	BLOCO_HORA : HORA port map (CLK_HORA, RESET, PRESETS(7 downto 4), PRESETS(3 downto 0), S_HORA, LOAD, INC, S5, S4);
	BLOCO_MINUTO : MINUTO port map (CLK_MINUTO, RESET, PRESETS(7 downto 4), PRESETS(3 downto 0), S_MINUTO, LOAD, INC, S3, S2, CLK_HORA);
	BLOCO_SEGUNDO : SEGUNDO port map (QCLK, RESET, PRESETS(7 downto 4), PRESETS(3 downto 0), S_SEGUNDO, LOAD, INC, S1, S0, CLK_MINUTO);
	TEMP : TEMPORIZADOR port map (QCLK, RESET, COUNT, AT);
	DIV_CLK : DIV_CLOCK port map (CLK, RESET, QCLK);
	
	ESTADO(2) <= S_HORA;
	ESTADO(1) <= S_MINUTO;
	ESTADO(0) <= S_SEGUNDO;

end DT_FLOW;